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Publication : Merging State and Preserving Timing Anomalies in Pipelines of High-End Processors

Authors : Sibin Mohan and Frank Mueller.

Abstract :

Many embedded systems are subject to temporal constraints that require advance guarantees on meeting deadlines. Such systems rely on static analysis to safely bound worst-case execution (WCET) bounds of tasks. Designers of these systems are forced to avoid state-of-the-art processors due to their inherent architectural complexity (such as out-of-order instruction scheduling) that results in non-determinism.

This work addresses this problem by providing novel
pipeline analysis techniques for characterizing the worst-case behavior of real-time systems on modern processor architectures. We introduce methods to capture (“snapshot”) pipeline state and to subsequently perform a “merge” of previously
captured snapshots. We prove that our pipeline analysis correctly preserves worst-case timing behavior on OOO processor pipelines. We further specifically show that anomalous pipeline effects, effectively dilating timing, are preserved by
our method. To the best of our knowledge, this method of pipeline analysis and interactions between hardware/software for obtaining WCET bounds on OOO processors is the first of its kind.

Here is a link to the full paper and slides to the talk at RTSS.

This was presented at the IEEE Real-Time Systems Symposium (RTSS), held in Barcelona in December 2008.

Also available as a Technical Report from NC State University.

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