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Moi...

I am currently working as a Visiting Research Scientist with Prof. Lui Sha, in the Dept. of Computer Science at the University of Illinois at Urbana Champaign (UIUC).

I currently work on the following topics:

  1. “Virtual Integration” techniques for complex systems (e.g.: Avionics)
  2. the integration of safety and security in safety-critical/real-time systems
  3. analysis of contemporary processor architectures to determine their worst-case behavior

My research interests are primarily in the Systems area. To be more specific: Embedded Systems, Cyber-Physical Systems (CPS), Real-Time Systems, System Integration, Security in Safety-Critical Systems, Avionics, Medical Devices, Computer Architecture, Operating Systems and Compilers.

I completed my Ph.D. in the Computer Science department at North Carolina State University, Raleigh. I worked with Dr. Frank Mueller on timing analysis and related techniques in the field of real-time and embedded systems. I have interned at Microsoft Research and Qualcomm and also worked at Hewlett-Packard in the past.

Proposals/Grants:

I am involved, as Senior Investigator, on three NSF proposals submitted from UIUC that are currently under review.

I contributed, significantly, to the writing of the following grants. I am also actively involved in the research that stems from them:


Read more about me.


News

[New] [Nov 2009] I am a program committee (PC) member for the Work in Progress (WIP) Session for the IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), 2010.

[New] [Oct. 2009] I am now a `Visiting Research Scientist’ in the Computer Science dept. at the University of Illinois at Urbana-Champaign (UIUC).

[New] [August 2009] My paper titled, “Rapid Early-Phase Virtual Integration” has been accepted at the IEEE Real-Time Systems Symposium (RTSS) conference to be held in Washington D.C in Dec. 2009.

[June 2009] My paper titled, “CheckerCore: Enhancing an FPGA Soft Core to Capture Worst-Case Execution Times” was published has been accepted at the Compilers Architectures and Systems for Embedded Systems (CASES) conference held in Grenoble, France in Oct. 2009. Jin Ouyang, a graduate student at Penn State, presented the paper.

All News...

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Research

My research interests are in the Systems area. To be more specific: Cyber-Physical Systems, Embedded and Real-Time Systems, Security, Computer Architecture, Operating Systems, Distributed Systems, and Compilers.

As part of my post-doctoral research at UIUC, I am investigating analysis techniques for safety-critical systems and system architecture design for medical systems, viz., Plug-n-Play Medical Devices. I am also investigating techniques for the worst-case analysis of avionics systems.

My dissertation work at NC State was aimed at characterizing the worst-case behavior for Real-Time Systems - I successfully dealt with analysis of modern architectural features. I also worked on microarchitectural modifications and design of processors for use in embedded and real-time systems.

Background | Real-Time Systems

Real-time schedulability analysis for any hard real-time system requires the WCET to be known beforehand and safely bounded. This is so that the feasibility of scheduling a task set can be determined given a scheduling policy.
Various approaches to determine the WCET of tasks exist, such as :

  • experimental methods, which are considered unsafe or constrained to probabilistic analysis.
  • Static analysis methods to derive safe WCET estimates.

Static methods model hardware components, e.g., the processor pipeline, caches, etc. They model the flow of code through various hardware components and use inter-procedural program representation and longest control-flow paths to obtain an upper bound on the number of cycles for any execution.

I have worked on timing analysis for the Atmel series of processors [1], parametric timing analysis and its applications to dynamic voltage scaling [2] in the past.

As part of my dissertation work, I developed a hybrid timing analysis scheme, where individual program paths are executed on actual hardware (microprocessors) and then combined to form the final, tight worst-case execution time on the software end.

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Publications List.

Thesis

Journal Publications

  1. Design of Wireless E-Healthcare Systems with Medical-Grade QoS by K. Kang, S. Mohan, K. Park, C. Kim and L. Sha to be submitted to the IEEE Networking Magazine.
  2. [pdf] Parametric Timing Analysis and its Application to DVS by S. Mohan and F. Mueller accepted for publication ACM TECS in 2008.

Conference Publications

  1. Time-Based Intrusion Detection in Cyber-Physical Systems by C. Zimmer, B. Bhatt, F. Mueller and S. Mohan to be submitted to IEEE RTAS 2010.
  2. Application Specific Integration Modular Avionics System Design with Tool Support by M. Nam, R. Pellizoni, S. Mohan, R. Bradford and L. Sha submitted to IEEE RTSS 2009.
  3. A Framework for Wireless Integration in Interoperable Real-Time Medical Systems by C. Kim, H. Yun, M. Sun, S. Mohan, A. Nayeem and L. Sha submitted to IEEE RTSS 2009.
  4. Component-based Description and Analysis for the Design of Real-Time Wireless System Architectures by K. Kang, W. Jeon, M. Nam, M. Yoon, S. Mohan, J. Kim and L. Sha submitted to IEEE RTSS 2009.
  5. Multi-Dimensional Fixed Point Loop Analysis for High End Embedded Processors by S. Mohan, R. Raghavendra and F. Mueller to be submitted to RTAS 2010.
  6. Rapid Early-Phase Virtual Integration by S. Mohan, M. Nam, R. Pellizoni, L. Sha, R. Bradford and S. Fliginger submitted to accepted for publication in  IEEE RTSS 2009.
  7. CheckerCore: Enhancing an FPGA Soft Core to Capture Worst-Case Execution Times by J. Ouyang, R. Raghavendra, S. Mohan, Y. Xie and F. Mueller accepted for publication in CASES 2009.
  8. [pdf] Push-Assisted Migration of Real-Time Tasks in Multi-Core Processors by A. Sarkar, F. Mueller, H. Ramaprasad and S. Mohan in LCTES 2009.
  9. [pdf] Merging State and Preserving Timing Anomalies in Pipelines of High-End Processors by S. Mohan and F. Mueller in IEEE RTSS 2008.
  10. [pdf] Hybrid Timing Analysis of Modern Processor Pipeline via Hardware/Software Interactions by S. Mohan and F. Mueller in IEEE RTAS 2008.
  11. [pdf] Temporal Analysis for Adapting Concurrent Applications to Embedded Systems by S. Mohan and J. Helander in ECRTS 2008.
  12. [pdf] ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling by S. Mohan, F. Mueller, W, Hawkins, M. Root, C. Healy and D. Whalley in IEEE RTSS 2005.
  13. [pdf] Timing Analysis for Sensor Network Nodes of the Atmega Processor Family by S. Mohan, F. Mueller, D. Whalley and C. Healy in IEEE RTAS 2005.

Workshop Publications

  1. Addressing Safety and Security Contradictions in Cyber-Physical Systems by M. Sun, S. Mohan, L. Sha and C. Gunter submitted to the Fourth Workshop on Embedded Systems Security (WESS) to be held as part of ESWeek in Oct. 2009.
  2. Integrating Security into Real-Time Systems using Temporal Constraints by C. Zimmer, F. Mueller and S. Mohan submitted to the Fourth Workshop on Embedded Systems Security (WESS) to be held as part of ESWeek in Oct. 2009.
  3. Addressing Safety and Security Contradictions in Cyber-Physical Systems by M. Sun, S. Mohan, L. Sha and C. Gunter. Position Paper. Published/presented at the First Workshop on Future Directions in Cyber-Physical Systems held in July 2009. This is a by-invitation only workshop.
  4. Time-Based Intrusion Detection in Cyber-Physical Systems by C. Zimmer, B. Bhatt, F. Mueller and S. Mohan published in the Work in Progress session at the EUROMICRO Conference on Real-Time Systems (ECRTS) held in Dublin, Ireland in July 2009.
  5. Building Robust Automotive Systems through Separation of Concerns by S. Mohan and J. Helander. Position paper at the National Workshop on High-Confidence Automotive Cyber-Physical Systems, April 2008. This is a by-invitation only workshop.
  6. [pdf] Worst-Case Execution Time Analysis of Security Policies for Deeply Embedded Real-Time Systems by S. Mohan at the PhD student forum in IEEE RTSS 2007. Published in ACM SIGBED Review Vol 5, Number 1 -- Special issue on the RTSS Forum on Deeply Embedded Real-Time Computing, January 2008.
  7. [pdf] CheckerMode: A Hybrid Scheme for Timing Analysis of Modern Processor Pipelines Involving Hardware/Software Interactions by S. Mohan and F. Mueller in IEEE RTAS WIP 2007.
Technical Reports
  1. Preserving Timing Anomalies in Pipelines of High-End Processors by S. Mohan and F. Mueller; North Carolina State University Dept. of Computer Science Technical Report, 2008 (TR-2008-13).
  2. Temporal Analysis for Adapting Concurrent Applications to Embedded Systems by S. Mohan and J. Helander; Microsoft Research Technical Report (MSR-TR-2008-37) 2008.
  3. Embedded Systems Research at DemoFest 2007 by O. Almeida, A. Forin, P. Garcia, J. Helander, N. Khantal, H. Lu, K. Meier, S. Mohan, H. Nielsen, R. Pittman, R. Serg, B. Sukhwani, M. Veanes, B. Zorn, S. Berry, C. Boyce, D. Chaszar, B. Culrich, M. Khisin, G. Knezeck, W. Linam-Church, S. Liu, M. Stewart and D. Toney; Microsoft Research Technical Report (MSR-TR-2007-94) 2007.
Posters
  1. Scalable Embedded Systems by J. Helander, R. Serg, S. Mohan, M. Veanes and P. Garcia at the RTSS 2007 Poster session, December 2007.
  2. Scalable Embedded Systems by J. Helander, R. Serg, S. Mohan, M. Veanes and P. Garcia at the Microsoft Faculty Summit DemoFest, Summer 2007.
  3. Static Timing Analysis for Sensor Nodes by S. Mohan and F. Mueller in the ACM SiGBED/SIGPLAN conference on Languages, Tools and Embedded Systems (LCTES) 2004.
Talks
[Note: In Computer Science, publications at top-ranking conferences are considered more important and prestigious than journals (of course they have their place as well). Here is an official memo from the Computing Research Association (CRA) stating that fact.

Some systems/real-time conference rankings: 1, 2, 3.
Of course, these not authoritative and not in any order, and they seem to have a slight bias towards US-based conferences. Some of the best work in systems (especially embedded/real-time systems) also happens in Europe, Singapore, etc.)]

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Professional Activities.

I am a member of ACM, IEEE, the IEEE Computer Society and ACM Special Interest group on Embedded Systems (SIGBED).

Program Committees

 

Paper Reviews

I have also participated in reviewing papers for the following Journals/conferences/workshops:

2009: IEEE TC, IEEE TPDS, ACM TECS

2008: ECRTS, LCTES, ISMM, RTSS, TII

2007: TII, LCTES, ICPP

2006: RTSS, ECRTS, ICPADS, RTCSA, WCET, HiPEAC

2005: RTSS, RTAS, LCTES, ECRTS, EMSOFT

2004: CASES, LCTES, ECRTS, CTCES, EMSOFT

 

Misc

I proposed and organized:

  • Panel discussion, "Preparing for a Faculty Career", Dept. of Computer Science, North Carolina State University
  • Mock interview sessions for prospective faculty candidates.
  • Workshop, "Effective Job Talks", Dept. of Computer Science, North Carolina State University

I have been an executive board member of the University Grad Students Association (UGSA) and the Computer Science Graduate Students Association (CSCGSA), at NC State, in the past.

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Real-Time Systems

A real-time system is is defined as a system that has both :
  • Logical, and
  • Temporal correctness.
The temporal correctness is defined in the form of a constraint, usually termed as deadline. The usefulness of results produced by the system drops significantly, at times, to zero, on the passing of this constraint.

Real-time systems are broadly classified into the following categories :
  • Hard : The usefulness of results on the passing of the contraint falls sharply and missing such constraints could lead to catastrophic effects to the system, then user, the environment, or all of them. Eg. : ABS system in cars, safety control of nuclear reactors, etc.
  • Soft : The usefulness of results falls gradually, on the passing of the constraint, and a few missed deadlines can be tolerated by the system, without catastrophic results. Eg. : MPEG decoding of streaming video.
A real-time system is defined as a collection of tasks, each of which is defined as : {phi, p, e, d}, where :
  • phi : phase
  • p : period
  • e : worst-case execution time of the task - the guaranteed upper bound on execution time of the task, for all possible inputs.
  • d : temporal constraint, deadline.
Real-time systems theory reasons about the schedulability of task sets i.e., offline schedulability tests, which can determine if all deadlines of a set of tasks can be met. Task parameters have to be known beforehand, i.e., parameters such as period of each task, the worst-case execution time (WCET), and so on. Periods of tasks are determined from the operating environment, such as temporal constraints on sensors, actuators and other parts of the system. Determining the WCET for tasks is a non-trivial effort due to software complexity, non-determinism of inputs and hardware complexity with unpredictable execution behavior.

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Publication : Push-Assisted Migration of Real-Time Tasks in Multi-Core Processors

Authors : Abhik Sarkar, Frank Mueller, Harini Ramaprasad and Sibin Mohan.

Abstract :

Multicores are becoming ubiquitous, not only in general-purpose but also embedded computing. This trend is a reflection of  contemporary embedded applications posing steadily increasing  demands in processing power. On such platforms, prediction of timing behavior to ensure that deadlines of real-time tasks can be  met is becoming increasingly difficult. While real-time multicore scheduling approaches help to assure deadlines based on firm theoretical properties, their reliance on task migration poses a significant challenge to timing predictability in practice. Task migration actually (a) reduces timing predictability for contemporary multicores due to cache warm-up overheads while (b) increasing traffic on the network-on-chip (NoC) interconnect.
This paper puts forth a fundamentally new approach to increase the timing predictability of multicore architectures aimed at task migration in embedded environments. A task migration between two cores imposes cache warm-up overheads on the migration target, which can lead to missed deadlines for tight real-time schedules.We propose novel micro-architectural support to migrate cache lines. Our scheme shows dramatically increased predictability in the presence of cross-core migration.
Experimental results for schedules demonstrate that our scheme enables real-time tasks to meet their deadlines in the presence of task migration. Our results illustrate that increases in execution time due to migration is reduced by our scheme to levels that may prevent deadline misses of real-time tasks that would otherwise occur. Our mechanism imposes an overhead at a fraction of the task’s execution time, yet this overhead can be steered to fill idle slots in the schedule, i.e., it does not contribute to the execution time of the migrated task. Overall, our novel migration scheme provides a unique mechanism capable of significantly increasing timing predictability in the wake of task migration.

Here is a link to the full paper and slides to the talk at RTSS.

This was presented at the ACM conference Languages, Compilers and Tools for Embedded Systems (LCTES), held in Dublin, Ireland in 2009.

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Ph.D. Thesis : Exploiting Hardware/Software Interactions for Analyzing Embedded Systems

Author : Sibin Mohan

Abstract :

Embedded systems are often subject to real-time timing constraints. Such systems require determinism to ensure that task deadlines are met. The knowledge of the bounds on worst-case execution times (WCET) of tasks is a critical piece of information required to achieve this objective. One limiting factor in designing real-time systems is the class of processors that may be used. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, and prefetching, cannot be statically analyzed to obtain WCETs for tasks as they introduce non-determinism into task execution, which can only be resolved at run-time. Such micro-processors are tuned to reduce average-case execution times at the expense of predictability. Hence, they do not find use in hard real-time systems. On the other hand, static timing analysis derives bounds on WCETs but requires that bounds on loop iterations be known statically, i.e., at compile time. This limits the class of applications that may be analyzed by static timing analysis and, hence, used in a real-time system. Finally, many embedded systems have communication and/or synchronization constructs and need to function on a wide spectrum of hardware devices ranging from small micro-controllers to modern multi-core architectures. Hence, any single analysis technique (be it static or dynamic) will not suffice in gauging the true nature of such systems.

This thesis contributes novel techniques that use combinations of analysis methods and constant interactions between them to tackle complexities in modern embedded systems. To be more specific, this thesis

(I) introduces of a new paradigm that proposes minor enhancements to modern processor architectures, which, on interaction with software modules, is able to obtain tight, accurate timing analysis results for modern processors;

(II) it shows how the constraint concerning statically bound loops may be relaxed and applied to make dynamic decisions at run-time to achieve power savings;

(III) it represents the temporal behavior of distributed real-time applications as colored graphs coupled with graph reductions/transformations that attempt to capture inherent “meaning” in the application.

To the best of my knowledge, these methods that utilize interactions between different sources of information to analyze modern embedded systems are a first of their kind.

 

Here is a link to the dissertation and the official Electronic Thesis and Dissertation link at the NC State University library.

This was submitted and accepted in August 2008.

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Publication : Merging State and Preserving Timing Anomalies in Pipelines of High-End Processors

Authors : Sibin Mohan and Frank Mueller.

Abstract :

Many embedded systems are subject to temporal constraints that require advance guarantees on meeting deadlines. Such systems rely on static analysis to safely bound worst-case execution (WCET) bounds of tasks. Designers of these systems are forced to avoid state-of-the-art processors due to their inherent architectural complexity (such as out-of-order instruction scheduling) that results in non-determinism.

This work addresses this problem by providing novel
pipeline analysis techniques for characterizing the worst-case behavior of real-time systems on modern processor architectures. We introduce methods to capture (“snapshot”) pipeline state and to subsequently perform a “merge” of previously
captured snapshots. We prove that our pipeline analysis correctly preserves worst-case timing behavior on OOO processor pipelines. We further specifically show that anomalous pipeline effects, effectively dilating timing, are preserved by
our method. To the best of our knowledge, this method of pipeline analysis and interactions between hardware/software for obtaining WCET bounds on OOO processors is the first of its kind.

Here is a link to the full paper and slides to the talk at RTSS.

This was presented at the IEEE Real-Time Systems Symposium (RTSS), held in Barcelona in December 2008.

Also available as a Technical Report from NC State University.

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Publication : Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions

Authors : Sibin Mohan and Frank Mueller.

Abstract :
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines for which knowledge of worst-case execution time (WCET) bounds is a critical piece of information. Static timing analysis techniques are used to derive these WCET bounds. A limiting factor for designing real-time systems is the class of processors that can be used. Typically, modern, complex processor pipelines cannot be used in real-time systems design. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, prefetching, etc., cannot be statically analyzed to obtain tight WCET bounds for tasks. The main reason is that these features introduce non-determinism to task execution that surfaces in full only at runtime.

In this paper, we introduce a new paradigm to perform timing analysis of tasks for real-time systems running on modern processor architectures. We propose minor enhancements to the processor architecture to enable this process. These features, on interaction with software modules, are able to obtain tight, accurate timing analysis results for modern processors. We also briefly present analysis techniques that, combined with our timing analysis methods, reduce the complexity of worst-case estimations for loops. To the best of our knowledge, this method of constant interactions between hardware and software to calculate WCET bounds for out-of-order processors is the first of its kind.

Here is a link to the full paper and slides to the talk at RTAS 2008.

This was published in the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), April, 2008.

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Publication : Temporal Analysis for Adapting Concurrent Applications to Embedded Systems

Authors : Sibin Mohan and Johannes Helander.

Abstract :
Embedded services and applications that interact with the real world often, over time, need to run on different kinds of hardware which range in capability from low-cost microcontrollers with very limited memory to powerful multicore processors. It is quite difficult to write one program that would work reliably on such a wide range of devices. This is especially true when the application must be temporally predictable and robust which should usually be the case since the physical world works in real-time. Thus, any application interacting with such a system, distributed or not, must also work in real-time.

In this paper we introduce a representation of the temporal behavior of an application as a colored graph that captures the timing of temporally continuous sections of execution, called bars, and the dependencies between the bars, creating a partial order. We then introduce a method of extracting the graph from existing applications using a combination of static, dynamic and other analyses. Once the graph has been created we employ a number of graph transformations, introduced here, that extract ``meaning'' from the graph. The knowledge gained can be utilized for scheduling and by the programmer for adjusting the level of parallelism suitable to the specific hardware, for identifying hot spots, false parallelism, or even candidates for additional concurrency. Graphs can be serialized to a partiture that can be used as input for offline, online, or even distributed real-time scheduling. Finally we present results from a prototype analyzer that was used on a complete TCP/IP stack in addition to smaller test applications. The most surprising outcome is that increasing the expression of concurrency can reduce the level of parallelism required, saving memory on deeply embedded platforms.

Here is a link to the full paper and slides to the talk at RTAS 2008.

This was published in the 20th EUROMICRO Conference on Real-Time Systems (ECRTS), July, 2008.

Also available as a Technical Report from Microsoft Research.

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Publication : Worst-Case Execution Time Analysis of Security Policies for Deeply Embedded Real-Time Systems

Authors : Sibin Mohan.

Abstract :
Deeply embedded systems often have unique constraints because of their small size and vital roles in critical infrastructure. Problems include limitations on code size, limited access to the actual hardware, {\em etc.} These problems become more critical in real-time systems where security policies must not only work within the above limitations but also ensure that task deadlines are not missed. A critical piece of information for security policies in real-time systems is the worst-case execution time (WCET) of the security code. This paper addresses some of the issues faced in the implementation of such security policies and also the process of determining WCETs for them. analysis safely bounds worst-case execution times to determine if tasks can meet their deadlines in hard real-time systems. However, conventional timing analysis requires that the upper bound of loops be known statically, which limits its applicability. Parametric timing analysis methods remove this constraint by providing the WCET as a formula parameterized on loop bounds.

Here is a link to the full paper, published in the ACM SIGBED Review, Vol. 5, Number 1 - Special issue on the RTSS Forum on Deeply Embedded Real-Time Computing.

This was presented at the PhD student forum of the IEEE Real-Time Systems Symposium (RTSS), held in December 2007.

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Publication : Parametric Timing Analysis and its Application to DVS

Authors : Sibin Mohan, Frank Mueller, William Hawkins, Michael Root, Christopher Healy, David Whalley and Emilio Vivancos.

Abstract :
Embedded Systems with real-time constraints depend on a-priori knowledge of worst-case execution times (WCETs) to determine if tasks meet deadlines. Static timing analysis derives bounds on WCETs but requires statically known loop bounds.

This work removes the constraints on known loop bounds through parametric analysis expressing WCETs as functions. Tighter WCETs are dynamically discovered to exploit slack by dynamic voltage scaling (DVS) saving 60%-80% energy over DVS-oblivious techniques and showing savings close to more costly dynamic-priority DVS algorithms.

Overall, parametric analysis expands the class of real-time applications to programs with loop-invariant dynamic loop bounds while retaining tight WCET bounds.

Here is a link to the full paper.

This has been accepted for publication in the ACM journal Transactions in Embedded Computing Systems (TECS) in 2008.

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Publication : CheckerMode : A hybrid scheme for timing analysis of modern processor pipelines involving hardware/software interactions

Authors : Sibin Mohan, Frank Mueller.

Abstract :

Real-time systems often require determinism to ensure that task deadlines are met. Schedulability analysis provides a firm basis to ensure that tasks deadlines are met, and for this, knowledge of bounds on worst-case execution times (WCET) of tasks is a critical piece of information. Static timing analysis derives these bounds on WCETs. A limiting factor for real-time systems design is the class of processors that may be used. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, and prefetching, cannot be statically analyzed to obtain WCETs for tasks because these features introduce non-determinism to task execution, which can only be resolved at run-time. We introduce a new paradigm which proposes minor enhancements to modern processor architectures, which, on interaction with software modules, is able to obtain tight, accurate timing analysis results for modern processors. To the best of our knowledge, this method of hardware/software interactions to calculate WCET results for out-of-order processors is the first of its kind.

Here is link to the full paper and slides to the talk at RTAS WIP 2007.

This was presented at the work-in-progress section of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), April, 2007.

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Publication : ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling

Authors : Sibin Mohan, Frank Mueller, William Hawkins, Michael Root, Christopher Healy and David Whalley.

Abstract :
Static timing analysis safely bounds worst-case execution times to determine if tasks can meet their deadlines in hard real-time systems. However, conventional timing analysis requires that the upper bound of loops be known statically, which limits its applicability. Parametric timing analysis methods remove this constraint by providing the WCET as a formula parameterized on loop bounds.

This paper contributes a novel technique to allow parametric timing analysis to interact with dynamic real-time schedulers. By dynamically detecting actual loop bounds, a lower WCET bound can be calculated, on-the-fly, for the remaining execution of a task. We analyze thebenefits from parametric analysis in terms of dynamically discovered slack in a schedule. We then assess the potential for dynamic power conservation by exploiting parametric loop bounds for ParaScale, our intra-task dynamic voltage scaling (DVS) approach. Our results demonstrate that the parametric approach to timing analysis provides significant savings, close to 66 \%, in terms of slack as well as power. We further show that using this approach combined with online intra-task DVS to exploit parametric execution times results in much lower power consumption. Hence, even in the absence of dynamic scheduling, significant savings in power can be obtained, e.g.,in the case of cyclic executives.

Here is a link to the full paper and the slides to the talk at RTSS 2005.

This was published in the IEEE Real-Time Systems Symposium (RTSS), December, 2005.

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Publication : Timing Analysis for Sensor Network Nodes of the Atmega Processor Family.

Authors : Sibin Mohan, Frank Mueller, David Whalley and Christopher Healy.

Abstract :
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor family used by Berkeley Motes lacks support for deriving safe bounds on the WCET, which is a prerequisite for performing real-time schedulability analysis. Our work fills this gap by providing an analytical method to obtain WCET bounds for this processor architecture.

Our first contribution is to analyze both C and NesC code, the latter of which is unprecedented. The second contribution is to model control hazards and variable-cycle instructions, both handled more efficiently by our approach than by previous ones and results in up to 77% improvement in bounding the WCET. The results demonstrate that our timing analysis framework is able to tightly and safely estimate the WCET of the benchmarks while simulator results are shown to not always provide safe WCET bounds. While motivated by the Atmel Atmega series of processors, results are equally applicable to low-end embedded processors.

This work is, to the best of our knowledge, the first set of experiments where timing results are contrasted from execution on an actual processor, from a cycle-accurate simulator and from a static timing analyzer. Furthermore, making our timing analysis toolset available to the Atmel Atmega processor family is a significant contribution towards addressing a documented need for tool support for sensor node architectures commonly used in networked systems of embedded computers, or so-called EmNets.

Here is a link to the full paper, and the slides to the talk at RTAS 2005.

This was published in the IEEE Real-Time and Embedded Systems and Application Symposium (RTAS), March 7-10, 2005.

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Personal

I am originally from the lovely city that is Bangalore, where I spent the first 23 years of my life!

I finished my undergrad degree from PES Institute of Technology in 2001.

My schooling, some of the best 14 years of my life, was spent at the Frank Anthony Public School.

Radha is the wonderful girl I got married to on August 19, 2007.

Context Switch is my blog where I put up random thoughts...

I was interviewed by Voice of America in early 2007.

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News

2009

[New] [Nov 2009] I am a program committee (PC) member for the Work in Progress (WIP) Session for the IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), 2010.

[New] [Oct. 2009] I am now a `Visiting Research Scientist’ in the Computer Science dept. at the University of Illinois at Urbana-Champaign (UIUC).

[New] [August 2009] My paper titled, “Rapid Early-Phase Virtual Integration” has been accepted at the IEEE Real-Time Systems Symposium (RTSS) conference to be held in Washington D.C in Dec. 2009.

[June 2009] My paper titled, “CheckerCore: Enhancing an FPGA Soft Core to Capture Worst-Case Execution Times” was published has been accepted at the Compilers Architectures and Systems for Embedded Systems (CASES) conference held in Grenoble, France in Oct. 2009. Jin Ouyang, a graduate student at Penn State, presented the paper.

[June 2009] My security paper titled, “Addressing Safety and Security Contradictions in Cyber-Physical Systems” was presented has been accepted at the First Workshop on Future Directions in Cyber-Physical Systems Security held in Newark, New Jersey.

[June 2009] My paper titled, “Push-Assisted Migration of Real-Time Tasks in Multi-Core Processors” has been accepted at was published in LCTES 2009 in Dublin, June 2009. Abhik Sarkar, a graduate student at NC State, presented the paper.

2008

[December 2008] I am now a program committee (PC) member for the 2nd International Workshop on Cyber-Physical Systems (WCPS) to be held in Montreal, Canada in June 2009.

[December 2008] I presented the paper titled, "Merging State and Preserving Timing Anomalies in Pipeline of High-End Processors" at the IEEE Real-Time Systems Symposium (RTSS) 2008 in Barcelona in December 2008.

[October 2008] I am a program committee (PC) member for the IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), 2009. This is one of the top two conferences in the field!

Started work as a post-doc with Prof. Lui Sha at UIUC.

[August 2008] Defended! Completed my Ph.D. and submitted my dissertation titled, "Exploiting Hardware/Software Interactions for Analyzing Embedded Systems".

[August 2008] My submission titled, "Merging State and Preserving Timing Anomalies in Pipeline of High-End Processors" has been accepted at RTSS 2008. I will be giving gave a talk at the conference in Barcelona in December 2008.

[March 2008] My submission titled, "Temporal Analysis for Adapting Concurrent Applications to Embedded Systems" has been accepted at ECRTS 2008. I gave a talk at the conference in Prague in July 2008.

[March 2008] I have received an invitation to attend the National Workshop on High-Confidence Automotive Cyber-Physical Systems to be held in April in Troy, Michigan. The call to attend this by-invitation only workshop was preceded by the submission of a position paper titled, "Building Robust Automotive Systems through Separation of Concerns," co-authored with Johannes Helander.

2007

[December 2007] My submission titled, "Hybrid Timing Analysis of Modern Processor Pipeline via Hardware/Software Interactions" has been accepted at IEEE RTAS 2008. I will be giving gave a talk at the conference in St. Louis in April 2008.

[December 2007] I gave a short talk on "Integrating Security Policies with Deeply Embedded Real-Time Systems" at an NSF planning workshop on Cyber Physical systems in the Automotive domain at RTSS 2007.

[December 2007] My submission to the RTSS PhD Forum on "Deeply Embedded Real-Time Computing" titled, "Worst-Case Execution Time Analysis of Security Policies for Deeply Embedded Real-Time Systems," has been accepted. I presented it at Tucson, Arizona on December 03, 2007.

[ September 2007] My journal submission was accepted for publication in the ACM TECS journal.

[August 2007] I interned in the Embedded Systems group at Microsoft Research in Redmond, Washington this summer (May-August 2007) which resulted in a paper submission to ECRTS 2008.

[April 2007] I have been awarded the prestigious "Preparing the Professoriate" fellowship by the NCSU Graduate School every year. Only 10 doctoral students are selected through a university-wide competition each year. This program brings doctoral students who are interested in an academic career together with experienced faculty members to improve their understanding of the teaching profession.

[April 28, 2007] Inspired by Dr. Tao Xie's Software Engineering Genealogy, I am working on creating a Real-Time Genealogy which lists researchers in the field of real-time systems. I also started a website for posting Real-Time Jobs (postdocs, etc.) and information about candidates looking for jobs.

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